1. Field of the Invention
The present invention is related to on-chip capacitors for Integrated Circuit (IC) chips and more particularly to integrated circuit chips with discrete capacitors on-chip.
2. Background Description
Integrated Circuits (ICs) are commonly made in the well-known complementary insulated gate Field Effect Transistor (FET) technology known as CMOS. Typical high performance ICs include CMOS devices (FETs) formed in a number of stacked layers (e.g., wiring, via, gate and gate dielectric) on a surface semiconductor (silicon) layer of a Silicon On Insulator (SOI) chip or wafer. CMOS technology and chip manufacturing advances have resulted in a steady decrease of chip feature size to increase on-chip circuit switching frequency (circuit performance) and the number of transistors (circuit density). In what is typically referred to as scaling, device or FET features are shrunk to shrink corresponding device minimum dimensions, including both horizontal dimensions (e.g., minimum channel length) and vertical dimensions, e.g., channel layer depth, gate dielectric thickness, junction depths and etc. Shrinking device size increases device density and improves circuit performance (both from increased device drive capability and decreased capacitive load). Scaling also entails thinning the surface device layer to control device threshold roll off. Especially in Ultra-Thin SOI (UTSOI), thinning the surface device layer has resulted in devices with fully depleted bodies (i.e., in what is known as Fully Depleted SOI or FD-SOI). Scaled FD-SOI devices can have substantially higher series resistance, as well as substantially higher capacitance.
Further, these CMOS circuits create current spikes from switching primarily capacitive FET circuit loads through impedance in the circuit/chip supply path. These current spikes may be reflected as noise on the chip supply that is known as supply or Vdd noise. High speed circuit switching may cause larger, narrower current spikes with very rapid rise and fall times. While scaling has increased device density with more devices/function per unit area, scaling has also resulted in, correspondingly, more devices switching per unit area at a significantly higher frequency. Supply noise can reduce circuit drive (i.e., because the circuit supply is reduced during such a supply spike) and even, under some circumstances, pass through to the output of a quiescent gate to appear that the gate is switching rather than quiescent. Since circuit switching is typically time varying, e.g., from clock cycle to clock cycle, the resulting noise also varies from cycle to cycle that can cause circuit responses to vary also with supply noise. Consequently, supply noise is a major chip design concern.
Decoupling capacitors (decaps), which are well known in the art, are used liberally at board level to reduce supply noise to a tolerable level. Decaps are small, low-resistance (high-Q), high-frequency capacitors, placed close to circuits being decoupled to reduce resistive losses, e.g., adjacent a module on a printed circuit board, adjacent a chip on a module, adjacent a circuit on a chip, and etc. Thus, decaps short circuit switching current at the module, chip or circuit. Unfortunately, prior art on-chip decaps are less effective in UTSOI due to higher series resistance.
Neither have such prior art on-chip capacitors been particularly suited to typical analog applications. Analog circuits frequently include discrete capacitors. A voltage controlled oscillator (VCO) in a phase-locked loop (PLL), for example, includes a capacitor in an RC filter to develop and filter a control voltage derived from the output frequency. The RC must have a time constant at least twice the VCO operating frequency for acceptable filtering. Unfortunately, typical state of the art capacitor structures formed with any substantial capacitance in a typical CMOS (e.g., UTSOI) technology have been inadequate and problematic.
Prior art discrete on-chip capacitor structures include an FET wired as a capacitor, typically called a MOSCAP. The drain and source diffusions of a MOSCAP FET are wired together to form one capacitor terminal and the FET gate is the other terminal. The MOSCAP per unit area capacitance is principally determined by the gate dielectric thickness. The MOSCAP electrical response is determined by its capacitance and the effective impedance between it and external circuitry. Conventional MOSCAP designs are, therefore, less effective in UTSOI, especially for high speed or fast switching applications, because of the larger time constant associated with the fully depleted FET body.
One alternative to the MOSCAP is the junction capacitor. Junction capacitors, in addition to being voltage varying, are leaky and form only at a PN junction, e.g., in the SOI surface layer. Typically such a junction capacitor includes a contact on the upper surface to a diffusion (i.e., a source/drain diffusion region) and a second contact to the other side of the junction at the surface layer adjacent to the diffusion. However, the junctions leak and capacitance for a junction capacitor is typically smaller than for the same sized MOSCAP. So, besides requiring larger areas for the same capacitance than MOSCAPS, the leaky junctions reduce their usefulness. Finally, because the UTSOI body is fully-depleted, it does not contain mobile charge. This lack of mobile charge means that the junction capacitor terminal at the body connection is ineffective.
Yet another alternative for a UTSOI capacitor is formed from adjacent wiring layers. Capacitors formed on adjacent wiring layers have, by comparison, low per unit area capacitance that may vary widely for very poor tolerance. Consequently, none of these prior art parallel plate capacitors are sufficiently dense or have a high enough per unit area capacitance for efficient decaps or vary to widely to be useful in UTSOI circuit design.
Thus, there is a need for on-chip high-Q capacitors suitable for analog circuit application or in decoupling (decaps) and, more particularly for smaller, denser discrete capacitors with low resistance plates and contacts directly available to both capacitor plates.